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Author(s) Title Year Proceedings
Edwards, S.A.; Kim, S.; Lee, E.A.; Liu, I.; Patel, H.D. & Schoeberl, M. IEEE A Disruptive Computer Design Idea: Architectures with Repeatable Timing 2009 Proceedings of IEEE International Conference on Computer Design (ICCD)  
Abstract: This paper argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.
BibTeX:
@article{pret:disruptive:09,
  author = {Stephen A. Edwards and Sungjun Kim and Edward A. Lee and Isaac Liu and Hiren D. Patel and Martin Schoeberl},
  title = {A Disruptive Computer Design Idea: Architectures with Repeatable Timing},
  booktitle = {Proceedings of IEEE International Conference on Computer Design (ICCD)},
  year = {2009},
  url = {http://chess.eecs.berkeley.edu/pubs/614.html}
}
					
Leung, M.-K.; Liu, I. & Zou, J. Code Generation for Process Network Models onto Parallel Architectures 2008 (UCB/EECS-2008-139)  
Abstract: With multi-core and many-core architectures becoming the current focus of research and development, and as vast varieties of architectures and programming models emerging in research, the design space for applications is becoming enormous. From the number of cores, the memory hierarchy, the interconnect to even the programming model and language used are all design choices that need to be optimized for applications in order to fully benefit from parallel architectures. We propose a code generation framework targeting rapid design space exploration and prototyping. From the high level design, code for specific architectures and mappings can be generated and used for comparison. We choose Khan Process Networks[11] as our current specification language, because of its inherit parallelism and expressiveness. Our code generator take advantage of Message Passing Interface (MPI) [6] as the API for implementing message passing across platforms. We show the scalability of the generated MPI code and the ability to extend our framework to allow for tuning and optimization.
BibTeX:
@article{Leung:EECS-2008-139,
  author = {Leung, Man-Kit and Liu, Isaac and Zou, Jia},
  title = {Code Generation for Process Network Models onto Parallel Architectures},
  year = {2008},
  number = {UCB/EECS-2008-139},
  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-139.html}
}
					
Lickly, B.; Liu, I.; Kim, S.; Patel, H.D.; Edwards, S.A. & Lee, E.A. Altman, E.R. (Hrsg.) Predictable programming on a precision timed architecture 2008 Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2008) , pp. 137-146  
Abstract: In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees. We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, inde- pendent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.
BibTeX:
@article{pret:cases:2008,
  author = {Ben Lickly and Isaac Liu and Sungjun Kim and Hiren D. Patel and Stephen A. Edwards and Edward A. Lee},
  title = {Predictable programming on a precision timed architecture},
  booktitle = {Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2008)},
  publisher = {ACM},
  year = {2008},
  pages = {137--146},
  url = {http://doi.acm.org/10.1145/1450095.1450117}
}
					
Liu, I.; Lickly, B.; Patel, H.D. & Lee, E.A. Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees 2009 IEEE Real-Time and Embedded Technology and Applications Symposium  
Abstract: We present our on-going efforts to guarantee the timing behavior of a program targeted for the precision timed architecture. We extend both the ISA and the hardware to support a set of timing instructions that allow programmers to control the execution time of a sequence of instructions. Programs written using these timing instructions specify deadlines within the program specification itself, and the hardware architecture enforces them through specific hardware policies. For example, timing instructions may be used to ensure that a segment of code has repeatable timing behavior, or that when a timing requirement is violated, an exception handler is invoked to appropriately address the timing violation. In this paper, we present the supported timing instructions, their semantics, and illustrative examples of their usage.
BibTeX:
@article{LiuLicklyPatelLee09_PosterAbstractTimingInstructionsISAExtensionsForTiming,
  author = {Isaac Liu and Ben Lickly and Hiren D. Patel and Edward A. Lee},
  title = {Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees},
  booktitle = {IEEE Real-Time and Embedded Technology and Applications Symposium},
  year = {2009},
  url = {http://chess.eecs.berkeley.edu/pubs/542.html}
}
					
Liu, I. & McGrogan, D. Elimination of Side Channel attacks on a Precision Timed Architecture 2009 (UCB/EECS-2009-15)  
Abstract: Side-channel attacks exploit information-leaky implementations of cryptographic algorithms to find the encryption key. These information leaks are caused by the underlying execution platform which contains hardware elements designed to optimize performance at the expense of predictable execution time. This shows that for security systems, not only does the software need to be secure, but the execution platform also needs to be secure in order for the entire system to be truly secure. PRET is an architecture designed for real time systems that has total predictability without sacrificing performance. It contains ISA extensions to bring total control over a program's temporal properties to the software level. We show that this design can not only defend against all software side channel attacks on encryption algorithms, but completely eliminate the root cause of the problem. We demonstrate this by running a reference implementation of the RSA algorithm on PRET and proving its immunity to side channel attacks.
BibTeX:
@article{pret:encryption:09,
  author = {Liu, Isaac and McGrogan, David},
  title = {Elimination of Side Channel attacks on a Precision Timed Architecture},
  year = {2009},
  number = {UCB/EECS-2009-15},
  note = {This a class project report describing early work on eliminating side channel attacks using PRET},
  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-15.html}
}
					

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my pic Isaac Liu is currently a software engineer at Apple Inc. working on the iOS performance team. He received his Ph.D in Electrical Engineering and Computer Science at the University of California, Berkeley . His research focus was in real time systems, parallel architectures and programming models. His thesis can be found here
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office 2 Infinite Loop, Cupertino, CA
email liu (dot) isaac (at) gmail (dot) com
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