Overview

My current research is on real-time embedded systems. Embedded systems are electronic systems which have special purposes, and are embedded into the platform to perform that special purpose. In contrary to conventional desktop computers, these systems are often resource constrained, which require optimization to use a limited amount of resources, or timing constrained, which means they need to perform the purpose in a certain amount of time (also called Real Time systems). For example, medical devices in humans or the braking system in an automobiles. The design of real time systems (or embedded systems in general) requires tight integration between software and hardware, thus it’s crucial to understand the whole system design stack. My current thesis (the PRET project) is focused on the hardware of the system, designing predictable architectures to ensure that software running on the system can be analyzed. The PRET project proposes a predictable computer architecture in which timing guarantees can be easily asserted.

Another research topic I’m working on is parallel architectures. As the single-core performance (and power) scaling is hitting a wall, multi/many-core systems are being designed to continue the improvement of performance. However, there are difficulties in both the software/hardware design of parallel computing systems. It’s difficult to reason about concurrency in software, so to effectively utilize the parallelism in hardware requires careful design of program structure. In the hardware, communication, interconnect and memory hierarchy all need careful design and thought, or else they might become an overhead and limit the performance increase of the system. This is especially troublesome for real time systems, as using a parallel computing system could easily thwart the timing predictability of the systems. My focus is on designing predictable real-time parallel systems, from the programming model to the parallel architecture.

Active Projects

PREcision Timed Machine (PRET) My main thesis project. This project focuses on designing a predictable and composable computer architecture to enable continued scaling of large scale concurrent real-time systems. Modern computer architectures have improved average case execution time at the cost of worst case execution time. Mechanisms such as caches and superscalar out-of-order execution pipelines result in hard to analyze worst case execution time. For the class of applications in which execution time needs to be guaranteed (the braking system of a car, or navigation system on a plane), this leads to major design issues. The PRET initiative proposes an alternate design goal for computer architectures – to design architectures with predictable timing behaviors. PRET introduces performance improvement mechanisms only when worst case predictability isn’t sacrificed. Techniques such as thread interleaved pipelines and scratchpad memories are employed to reconcile performance and predictability. We envision that only with a timing predictable computer architecture such as PRET, will we be able to continue scaling up designs for future real-time systems.

Programming Temporally Integrated Distributed Embedded Systems (PTIDES) PTIDES focuses on designing a programming model for distributed real time systems. The semantics of the programming model is built on top of the discrete event semantics, where actors have tasks, and are triggered by receiving and sending events. Each event is tagged with a time-stamp, which actors and manipulate to specify deadlines. I worked partly on PtidyOS, which is a ultra light weight real time operation system that realizes PTIDES. By using

Ptolemy Ptolemy is a software infrastructure our research group maintains used to do research on different models of computation. It contains a graphical user interface where users can experiment with different programming models. Ptolemy uses an actor oriented programming, where programs are constructed of actors which communicate only through ports. Actors perform tasks, and the communication between then depends on the model of computation. Ptolemy is written completely in Java, and is completely open source. It contains several directors which control the model of computation (Dataflow, Discrete Event, Continuous Time, Finite State Machine…) for different models. It also provides hierarchical composition of different models of computations enabling design and modeling of hybrid systems. There is also a code generation framework that can generate C code to execute on any underlying platform that has a c compiler and supports threads.

Past Projects

Code Generation for Parallel Systems MPI (Message Passing Interface) is a library written for parallel applications. It passes data between different threads explicitly through library calls. This project analyzes a higher level programming model – Synchronous Dataflow, and treats each actor as a thread. It then code generates the communication mechanism between actors using MPI. This way you can run a Dataflow model on a parallel architecture and let MPI take care of the communication.

Side Channel Attacks for Encryption Systems This project deals with the vulnerability of encryption algorithms when being attacked through side channels. Although mathematically the encryption algorithms are sound, but the underlying hardware architecture that the encryption runs on leaks valuable information that can lead to deciphering the key. Such examples are run time and power usage of each run of the algorithm. We deal with the execution time vulnerability of the encryption algorithm and propose for embedded applications that a Precision Timed Machine should be used to control the execution time of the algorithm. Porting several encryption algorithms onto the PRET architecture, we show that the run time of the algorithm on PRET show no correlation to the encryption key, securing it from side channel attacks stemming from execution time measurement.

my pic Isaac Liu is currently a software engineer at Apple Inc. working on the iOS performance team. He received his Ph.D in Electrical Engineering and Computer Science at the University of California, Berkeley . His research focus was in real time systems, parallel architectures and programming models. His thesis can be found here
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office 2 Infinite Loop, Cupertino, CA
email liu (dot) isaac (at) gmail (dot) com
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